Fast feedthrough logic a high performance logic family for GaAs
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Abstract
A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input signals arrive. A modified version of this logic, where the function and its complement are implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are reset to low during the high phase of the clock and evaluated during the low phase of the clock. Resetting to low alleviates the problems of charge sharing and leakage current associated with the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like fashion without a need for the intervening inverters. We employ this novel concept to design several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other published works in terms of device count, area, delay, clock rate and power consumption. The results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition, our FTL design compares very well with the standard CMOS technology. FTL gates are fully compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be included in a DCFL standard cell library for improving cell-based ASIC performance. To match the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining the FTL blocks. Comparisons with the other published results demonstrate the superior performance of our dynamic latch.
翻譯
快速傳送到邏輯高性能的邏輯家族的材料
文摘
一種材料動(dòng)態(tài)邏輯家庭使用的概念是流經(jīng)評價(jià)進(jìn)行了闡述。通過飼料邏輯(整車)允許的輸出部分的輸入信號產(chǎn)生之前到達(dá)。這一邏輯的修改版本,功能及其實(shí)現(xiàn)差分互補(bǔ)結(jié)構(gòu),進(jìn)行了介紹。在一個(gè)整車門、邏輯輸出改為低在高階段的時(shí)鐘和評估,在低相位的時(shí)鐘。重置到較低的問題,緩解的共享和泄漏電流與其它材料動(dòng)態(tài)邏輯家族。整車邏輯函數(shù)可以在一個(gè)骨牌一樣逆變器沒有必要時(shí)尚的干預(yù)。我們使用這個(gè)新概念到設(shè)計(jì)的幾個(gè)運(yùn)算電路。我們比較了4比特脈動(dòng)進(jìn)行整車與其他的調(diào)皮的裝置作品數(shù)、區(qū)、延誤,時(shí)鐘速率和功耗。結(jié)果表明,整車是最簡單、最快的,且消耗最小力量。此外,整車設(shè)計(jì)比較與標(biāo)準(zhǔn)的CMOS技術(shù)。比爾·蓋茨是完全相容于整車耦合場效應(yīng)晶體管邏輯直接(DCFL),因此,可以包含在一個(gè)DCFL標(biāo)準(zhǔn)電池性能提高基于圖書館集成電路。匹配的快速的整車組合塊,我們提出了一個(gè)結(jié)束單人賽門閂,流水線的區(qū)塊。整車與其他出版的比較驗(yàn)證性能優(yōu)越的動(dòng)態(tài)的門閂。
Combined regressor methods and adaptive IIR filtering
Abstract
An open issue in adaptive infinite-impulse response (IIR) filtering is that of convergence to a global minimum in the presence of observation noise when the system is insufficiently modeled . It is well known , that algorithms based on equation error (EE) formulation contain a single minimum that may be biased whereas, algorithms based on output error (OE) ensure the existence of an unbiased global minimum in presence of local minima. Recently, there have been several attempts to combine these formulations in order to ensure the existence and uniqueness of an unbiased minimum. Works presented here, EEOE and modified EEOE (MEEOE), are such attempts in the context of system identification. We will show, analytically and through simulations, the convergence properties of the MEEOE approach, in the context of system identification.
翻譯
結(jié)合檢索方法和自適應(yīng)濾波成立
開放的問題無限的沖動(dòng)自適應(yīng)濾波的回應(yīng)(檢索)的全球最低的收斂存在觀測噪聲時(shí),該系統(tǒng)還不夠。眾所周知,基于方程的算法誤差(EE)配方含有一個(gè)最小的,可能是偏見而算法根據(jù)輸出誤差(部分),保證了存在的一個(gè)無偏全球最低的局部最小值。最近,有幾次嘗試把這些配方,以確保解的存在唯一性的無偏最小。這里介紹,EEOE作品和修改EEOE(MEEOE),這樣的嘗試語境中的系統(tǒng)識別。我們將顯示,分析并通過模擬、收斂性能的方法,MEEOE語境中的系統(tǒng)識別。
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